The semiconductor industry continually strives to increase device performance and device density by reducing device dimensions. In addition, it is also desirable to increase the functionality of integrated circuits by incorporating multiple devices within the same integrated circuit. For a given chip size, device density can be increased by reducing the lateral distance separating active devices, or the device isolation width. Thus, advanced integrated circuits require a variety of devices to be integrated into the same integrated circuit without compromising the electrical isolation between adjacent active devices.
These advanced integrated circuits often include a variety of devices, each having a specific performance criteria. For example, an integrated circuit which includes both digital logic and non-volatile memory will require transistors having a high breakdown voltage to program the non-volatile memory and fast transistors having a lower breakdown voltage for digital logic. Likewise, a microprocessor integrated circuit having a low voltage core that interfaces with higher voltage peripherals will require transistors having a high breakdown voltage for the input/output (I/O) interface and transistors having a lower breakdown voltage for the core. Therefore, within an integrated circuit there may be multiple devices with differing breakdown voltage requirements. Thus, it is highly desirable to form high breakdown voltage transistors and low breakdown voltage transistors in the same integrated circuit without compromising the electrical isolation of either device.
The gate oxide layer of a transistor with a low breakdown voltage is typically thinner than the gate oxide layer of a transistor with a high breakdown voltage. Therefore, the formation of integrated circuits with both high breakdown voltage transistors and low breakdown voltage transistors requires two different gate dielectric layers to be formed. In addition, an integrated circuit having memory devices may require a third gate dielectric layer to be formed. The processes used to form these multiple gate dielectric layers, however, recess or thin the isolation region that lies between adjacent active devices, and thus electrical isolation between adjacent active devices is adversely effected by these processes. In addition, recessing of trench isolation regions during gate dielectric formation processes results in the formation of parasitic transistors along the trench sidewall which increase device leakage currents and result in the formation of inferior gate dielectric layers.
Accordingly, a need exists for a method of forming integrated circuits with multiple gate dielectric layers without degrading device isolation.